Alexander Pfriem

+49 / 931 / 418-2269


How to Design Mission Critical & Reliable FPGA & SoC

3-Tages-Seminar (Hands-On)

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Zum Thema

FPGA’s and heterogeneous SoC’s are used in an increasing number of mission critical or high reliability applications. These applications span a diverse range from industrial, medical and scientific to defences, transportation and even space. For these devices to safely and reliability operate in an often-harsh environment, a more rigorous design approach is required. One that introduces both stricter engineering governance in the design process and design mitigation techniques.

As such designing these solutions requires the designer to not only understand what techniques can be used at the logic level but also, the wider systematic, regulatory and environmental issues.


This seminar will therefore present the environmental challenges and what they mean to the logic designer. Along with introducing high level concepts such as SIL level, Reliability and Mean Time to Failure, attendees will also gain an understanding of the importance of engineering governance.

The focus of this seminar is the development of techniques which can be used in programmable logic including Clocking & Reset strategy, Triple Modular Redundancy, IO Planning, Safe State Machines and Counters, Error Correcting Codes along with Verification strategies and metrics, formal equivalence checking, Synthesis strategies and several other advanced techniques.


  • Section One - Challenges
    • How the environment impacts our designs
  • Section Two – Programmatic / System level considerations.
    • Different Standards 61508 / DO254 / ISO 26262
    • Failure Space
    • The design life cycles
    • Engineering Governance
    • What is reliability?
    • What does MTBF Mean?
    • What impacts the MTBF?
    • Requirement capture
    • Architectural design
    • Inter dependency of faults between SW and HW
    • Interface Control Definitions
    • Verification
    • Redundancy
    • Failure Mode
    • Common Cause Failures
    • Worse Case Analysis
  • Section Three – FPGA Design Considerations
    • FPGA Development overview
    • Module Documentation, Description, Test Plan
    • Coding Style
    • Certified tools
    • Self-Test and Diagnostics (CBT, PBIT, DIT)
    • Clocks and Reset
    • IO Planning
    • JTAG / Boundary Scan
    • Failure modes of modules Stuck at failure modes
    • Safer State Machines – How to develop state machines for higher reliability applications
    • Safer Counters Example
    • Error Correcting Codes - Use in Memories
    • Synthesis & Formal Equivalence checking
    • Verification – how to achieve functional coverage.
    • Verification Metrics
    • Fault Injection
    • Timing Closure
  • Labs
    • Common Cause Failure Identification
    • Safe State Machine
    • Fault Injection test bench development

Target Audience

This seminar adresses FPGA Designer and FPGA Project Leader.


This seminar will be held in English.


Adam Taylor

ptek GmbH | Geschäftsführer

Adam Taylor is an expert in design and development of embedded systems and FPGA’s for several end applications. Throughout his career, Adam has used FPGA’s to implement a wide variety of solutions from RADAR to safety critical control systems, with interesting stops in image processing and cryptography along the way. Most recently he was the Chief Engineer of a Space Imaging company, being responsible for several game changing projects. Adam is the author of numerous articles on electronic design and FPGA design including over 200 blogs on how to use the Zynq for Xilinx. Adam is Chartered Engineer and Fellow of the Institute of Engineering and Technology



05.06.2019 | 09:00 - 17:00 Uhr
06.06.2019 | 09:00 - 17:00 Uhr
07.06.2019 | 09:00 - 17:00 Uhr

Zur Anmeldeseite

06.11.2019 | 09:00 - 17:00 Uhr
07.11.2019 | 09:00 - 17:00 Uhr
08.11.2019 | 09:00 - 17:00 Uhr

Zur Anmeldeseite




Fragen, Wünsche & Anregungen

Alexander Pfriem
Event Manager
E-Mail: alexander.pfriem@vogel.de
Tel:+49 / 931 / 418-2269


1.900,00 € zzgl. MwSt.

In der Teilnahmegebühr sind die Unterlagen, die Getränke, die Pausenerfrischungen, das Mittagessen sowie ein Teilnahmezertifikat enthalten.
Rabattregelung: Wenn Sie gleichzeitig zwei oder mehr Anmeldungen vornehmen, erhalten Sie ab der zweiten Buchung 10 % Rabatt auf den Preis.

Maximale Teilnehmerzahl

Um ein optimales Lernergebnis zu erzielen und den Austausch zwischen Referent und Teilnehmern sowie den Teilnehmern untereinander zu gewährleisten, beträgt die maximale Teilnehmerzahl für dieses Seminar 12 Personen.


Sollten Sie bis zur ersten Mittagspause feststellen, dass das Seminar Ihren Erwartungen nicht gerecht wird, dann können Sie es verlassen. Die bereits gezahlte Gebühr erstatten wir Ihnen dann zurück. Bitte informieren Sie uns in diesem Fall umgehend.

Zur Anmeldeseite

05.06.2019 - 07.06.2019Hamburg

06.11.2019 - 08.11.2019Frankfurt


1.900,00 € zzgl. MwSt.


Bitte sprechen Sie mich an, wenn Sie Fragen, Anregungen, Lob oder Kritik zu unseren Seminaren haben.

Alexander Pfriem
Projektleitung Seminare
Tel: +49 / 931 / 418-2269
E-Mail: alexander.pfriem@vogel.de

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